Q1> In a combinational circuit ,there are 2 inputs X=X3 X2 X1 X0 & Y= Y3 Y2 Y1 Y0. There is a 4 bit comparator circuit is available shown Below with a multiplexer whose 8 inputs used as inputs and has 4 outputs. Design a circuit so that when C=0 then output of multiplexer is Min(X,Y) and when C=1 the output of mux is Max (X,Y). You can use some more Additional gates as required.
Figure is in :
Q2> Design a Ones counter circuit has 7 Inputs X0,X1,X2,X3,X4,X5,X6 and has 3 outputs O3 O2 O1. Thus ones’s counter gives 3 bit output which is equal to numbers of 1s in the inputs.
Q3> Develop a state Table / Flow design a for the circuit given below,
It has one input teminal x & and one input terminal ‘z’. The output ‘z’ =1 whenever the input recievs EVEN numbers of ‘0’s (Except 1st zero) . If current receiving input =’0’ and is even then only output is ‘1’ otherwise ‘0’.
Ocuurance off “11” is avoided,but if occurs then output remains 0 afterwards.
000001010011101……..
010100110110000…….
Q4> There is a ram available of 8x2 as shown below. Arrange these ,so that we get 16x4 RAM with use of Same additional gates a reqired.
Q5> Generate a memory mapping of a circuit:
Figure is in:
Other Questions where all about State machine but I can remember those cause they were very tricky and no time was there to understand properly .
Q> All were like, there is a input X of 2 or 3 bits, when X1X0 becomes 00 thrice in any order in incoming data , then output is 1 but when “11” comes thrice output becomes zero.
Q> State machine having 2 input X1 x0 and 2 output, for some combination of input ,there will be some input and for other it will be different and like this only.
